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? semiconductor components industries, llc, 2002 september, 2002 rev. 3 1 publication order number: nbsg86a/d nbsg86a 2.5v/3.3vsige differential smart gate with output level select the nbsg86a is a multifunction differential logic gate which can be configured as an and/nand, or/nor, xor/xnor, or 2:1 mux. this device is part of the gigacomm ? family of high performance silicon germanium products. the device is housed in a low profile 4x4 mm, 16pin, flipchip bga package. differential inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), cmos, cml, or lvds. the ols input is used to program the peaktopeak output amplitude between 0 and 800 mv in five discrete steps. the nbsg86a employs input clamping circuitry so that under open input conditions the outputs of the device will remain stable. ? maximum input clock frequency > 8 ghz typical ? 165 ps typical propagation delay ? 40 ps typical rise and fall times ? selectable swing pecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? selectable swing necl output with necl inputs with operating range: v cc = 0 v with v ee = 2.375 v to 3.465 v ? digitally selectable output level select (0 v, 200 mv, 400 mv, 600 mv, or 800 mv peaktopeak output) ? 50 (to v tt ) internal input termination resistors l = wafer lot y = year w = work week *for further details, refer to application note and8002/d fcbga16 ba suffix case 489 marking diagram* sg 86a device package shipping ordering information nbsg86aba 4x4 mm fcbga16 100 units/tray nbsg86abar2 4x4 mm fcbga16 500/ tape & reel lyw board description sg86abaevb nbsg86aba evaluation board http://onsemi.com
nbsg86a http://onsemi.com 2 q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel vtd1 sel sel ols vtd0 d0 vtsel d1 d1 vtd1 v cc v ee d0 vtd0 q q a b c d 12 34 pin description pin d0*, d1*, d0 **, d1 ** q, q data outputs function data inputs v cc positive supply v ee negative supply vtd0, vtd0 , vtd1, vtd1 50 internal input termination resistor vtsel 50 internal input termination resistor connected to sel and sel sel, sel select inputs ols (output level select) input * pin will default low when left open. ** pin will default to a slightly higher potential than d0/d1 when both are left open. figure 1. pinout (top view) figure 2. logic diagram d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel figure 3. configuration for and/nand function v cc vt or vbb d0 d0 d1 d1 and/nand truth table** 0 0 0 0 d0 0 0 1 1 d1 0 1 0 1 sel * 0 0 0 1 q output level select (ols) ols v cc v cc 0.4 v 200 mv q/q vpp 800 mv float 600 mv v cc 0.8 v 600 mv v cc 1.2 v 0 v ee * 400 mv * when an output level of 400 mv is desired and v cc v ee > 3.0 v, 2.0 k resistor should be connected from ols to v ee . ols 150 mv ols sensitivity ols 75 mv n/a ols 100 mv ols 75 mv ols + 100 mv ** d0 , d1 , sel are inverse of d0, d1, sel unless specified otherwise.
nbsg86a http://onsemi.com 3 d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel d0 d0 d1 d1 figure 4. configuration for or/nor function figure 5. configuration for xor/xnor function figure 6. configuration for 2:1 mux function 1 0 0 d1 0 1 0 1 sel xor 0 1 1 0 q xor/xnor truth table** 0 0 1 1 d0 1 or/nor truth table** 0 0 1 1 d0 1 1 1 1 d1 0 1 0 1 sel or 0 1 1 1 q d1 d0 q 2:1 mux truth table q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel v cc vt or vbb d0 d0 d1 d1 1 0 sel ** d0 , d1 , sel are inverse of d0, d1, sel unless specified otherwise. ** d0 , d1 , sel are inverse of d0, d1, sel unless specified otherwise.
nbsg86a http://onsemi.com 4 interfacing options connections cml connect vtd0, vtd1, vtsel and vtd0 , vtd1 to v cc lvds connect vtd0, vtd1, vtd0 and vtd1 together. leave vtsel open. accoupled bias vtd0, vtd1, vtsel and vtd0 , vtd1 inputs within (vihcmr) common mode range rsecl, pecl, necl standard ecl termination techniques attributes characteristics value internal input pulldown resistors 75 k internal input pullup resistor (d ) 37.5 k esd protection human body model machine model charged device model > 1 kv > 50 v > 4 kv moisture sensitivity (note 1) oxygen index: 28 to 34 level 3 flammability rating ul 94 v0 @ 0.125 in transistor count 364 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 3.6 v v v inpp (inin) differential input voltage swing/sensitivity v cc v ee 2.8 v v cc v ee < 2.8 v 2.8 |v cc v ee | v v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma ta operating temperature range 40 to +70 c t stg storage temperature range 65 to +150 c ja thermal resistance (junctiontoambient) (note 3) 0 lfpm 500 lfpm 16 fcbga 16 fcbga 108 86 c/w c/w jc thermal resistance (junctiontocase) 2s2p (note 3) 16 fcbga 5 c/w t sol wave solder 15 sec. 225 c 2. maximum ratings are those values beyond which device damage may occur. 3. jedec standard multilayer board 2s2p (2 signal, 2 power)
nbsg86a http://onsemi.com 5 dc characteristics, input with pecl output v cc = 2.5 v; v ee = 0 v (note 4) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 30 39 23 30 39 23 30 39 ma v oh output high voltage (note 5) 1460 1510 1560 1490 1540 1590 1515 1565 1615 mv v ol output low voltage (note 5) (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1355 1015 1555 1185 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1390 1050 1590 1220 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1415 1080 1610 1245 mv v outpp output pp voltage (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 715 125 525 0 325 805 215 615 5 415 705 120 520 0 320 795 210 610 0 410 700 120 515 0 320 790 210 605 5 410 mv v ih input high voltage (singleended) (note 7) d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (note 8) d, d v ee v cc 1400* v ih 150 v ee v cc 1400* v ih 150 v ee v cc 1400* v ih 150 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) d, d sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel 20 5 100 50 20 5 100 50 20 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to 0.965 v. 5. all loading with 50 to v cc 2.0 volts. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v ih cannot exceed v cc . 8. v il always v ee . *typicals used for testing purposes.
nbsg86a http://onsemi.com 6 dc characteristics, input with pecl output v cc = 3.3 v; v ee = 0 v (note 9) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 30 39 23 30 39 23 30 39 ma v oh output high voltage (note 10) 2260 2310 2360 2290 2340 2390 2315 2365 2415 mv v ol output low voltage (note 10) (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2150 1790 2360 1965 1360 2065 1585 2290 1820 1510 2125 1705 2340 1910 1660 2185 1825 2390 2000 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2210 1855 2415 2030 mv v outpp output pp voltage (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 750 130 550 0 345 840 220 640 0 435 740 125 545 0 340 830 215 635 0 430 735 125 540 0 335 825 215 630 0 425 mv v ih input high voltage (singleended) (note 12) d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (note 13) d, d v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 mv v ihcmr input high voltage common mode range (differential) (note 11) 1.2 3.3 1.2 3.3 1.2 3.3 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) d, d sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel 20 5 100 50 20 5 100 50 20 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 9. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to 0.165 v. 10. all loading with 50 to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 12. v ih cannot exceed v cc . 13. v il always v ee . *typicals used for testing purposes. **when an output level of 400 mv is desired and v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg86a http://onsemi.com 7 dc characteristics, necl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 14) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 30 39 23 30 39 23 30 39 ma v oh output high voltage (note 15) 1040 990 940 1010 960 910 985 935 885 mv v ol output low voltage (note 15) 3.465 v v ee 3.0 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 3.0 v < v ee 2.375 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 1980 1270 1750 1040 1515 1945 1265 1725 1045 1495 1830 1210 1630 990 1425 1795 1205 1605 995 1405 1680 1150 1510 940 1335 1645 1145 1485 945 1315 1940 1235 1715 1010 1480 1905 1230 1690 1010 1460 1790 1175 1595 960 1390 1755 1170 1570 960 1370 1640 1115 1475 910 1300 1605 1110 1450 910 1280 1910 1210 1685 985 1450 1875 1205 1660 990 1435 1760 1150 1565 935 1360 1725 1145 1540 940 1345 1610 1090 1445 885 1270 1575 1085 1420 890 1255 mv v outpp output pp voltage 3.465 v v ee 3.0 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 3.0 v < v ee 2.375 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 750 130 550 0 345 715 125 525 0 325 840 220 640 0 435 805 215 615 5 415 740 125 545 0 340 705 120 520 0 320 830 215 635 0 430 795 210 610 0 410 735 125 540 0 335 700 120 515 0 320 825 215 630 0 425 790 210 605 5 410 mv v ih input high voltage (singleended) (note 17) d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (note 18) d, d v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 mv v ihcmr input high voltage common mode range (differential) (note 16) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current (@v ih ) d, d sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel 20 5 100 50 20 5 100 50 20 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained . 14. input and output parameters vary 1:1 with v cc . 15. all loading with 50 to v cc 2.0 volts. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 17. v ih cannot exceed v cc . 18. v il always v ee . *typicals used for testing purposes. **when an output level of 400 mv is desired and v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg86a http://onsemi.com 8 ac characteristics v cc = 0 v; v ee = 3.465 v to 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 7 f max /jitter) (note 19) 7 8 7 8 7 8 ghz t plh , t phl propagation delay to output differential d/sel q 110 160 210 115 165 215 120 170 220 ps t skew duty cycle skew (note 20) 5 15 5 15 5 15 ps t skew channel skew q d/sel 5 20 5 20 5 20 ps t jitter random clock jitter (rms) (see figure 7. f max /jitter) (note 19) 0.5 1.5 0.5 1.5 0.5 1.5 ps v inpp input voltage swing/sensitivity (differential) (note 21) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% 80%) (q, q ) 20 40 65 20 40 65 20 40 65 ps 19. measured using a 500 mv source, 50% duty cycle clock source. all loading with 50 to v cc 2.0 v. 20. t skew = |t plh t phl | for a nominal 50% differential clock input waveform. see figure 8. 21. v inpp (max) cannot exceed v cc v ee .
nbsg86a http://onsemi.com 9 rms jitter frequency (ghz) output amplitude (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 12345678910 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc 0.4 v *ols = v ee ols = v cc 0.8 v ols = float rms jitter frequency (ghz) output amplitude (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 12345678910 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc 0.4 v *ols = v ee ols = v cc 0.8 v, ols = float figure 7. v out /jitter vs. frequency for 2:1 mux mode (v cc v ee = 2.5 v @ 25 c; repetitive 1010 input data pattern) figure 8. v out /jitter vs. frequency for 2:1 mux mode (v cc v ee = 3.3 v @ 25 c; repetitive 1010 input data pattern)
nbsg86a http://onsemi.com 10 i ols ( a) 700 600 500 400 300 200 100 0 100 200 300 figure 9. typical ols input current vs. ols input voltage (v cc v ee = 3.3 v @ 25 c) v ols (mv) v outpp (mv) 0 200 400 600 800 1000 ols (mv) figure 10. ols operating area v ee v cc v cc 400 v cc 800 v cc 1200 v ee v cc v cc 400 v cc 800 v cc 1200 v cc 75 v cc 250 v cc 550 v cc 700 v cc 900 v cc 1125 v cc 1275 v ee + 100
nbsg86a http://onsemi.com 11 figure 11. ac reference measurement d d q q t phl t plh v pp d v tt = v cc 2.0 v driver device receiver device qd 50 50 v tt figure 12. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices) q
nbsg86a http://onsemi.com 12 package dimensions fcbga16 ba suffix plastic 4 x 4 (mm) bga flip chip package case 48901 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view mm e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k x y m m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 291 kamimeguro, meguroku, tokyo, japan 1530051 phone : 81357733850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg86a/d gigacomm is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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